SCANNING VOL. 24, 86–91 (2002)
Received: January 26, 2000
Accepted with revision: December 27, 2001
© FAMS, Inc.

Automatic Integrated Circuit Die Positioning in the Scanning Electron Microscope

H.W. Tan, J.C.H. Phang, J.T.L. Thong

Centre for Integrated Circuit Failure Analysis and Reliability (CICFAR), Faculty of Engineering, National University of Singapore, Singapore

Full-text (for Scanning subscribers)

Summary: In scanning electron microscope (SEM)-based integrated circuit (IC) failure analysis, there is often a need for manual location of a prespecified failure site in several ICs. Such a procedure is both tedious and time consuming. This paper presents a new vision-based die positioning system that can automatically locate a specified failure site without the need for a high-accuracy specimen stage. Depending on the appearance of the desired failure site, the system applies either image registration or feature tracking to locate the site. Experiments performed on a variety of IC samples show that the system is able to locate the failure site accurately, even in the presence of unfavorable conditions such as IC sample rotation and repetitive IC patterns.

Key words: die positioning, scanning electron microscopy, registration, template matching, automation

PACS: 61.16.Bg, 06.60.Sx, 07.60.Pb, 07.05.Pj

This work was supported by an NSTB grant no. NSTB/17/2/3.

Address for reprints:
John T. L. Thong
Centre for Integrated Circuit Failure Analysis and Reliability (CICFAR)
Faculty of Engineering
National University of Singapore
4 Engineering Drive 3
Singapore 117576